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The UVM Primer

The UVM Primer [Kindle Edition]

Ray Salemi

Kindle-Preis: EUR 29,18 Inkl. MwSt. und kostenloser drahtloser Lieferung über Amazon Whispernet

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The UVM Primer uses simple, runnable code examples, accessible analogies, and an easy-to-read style to introduce you to the foundation of the Universal Verification Methodology. You will learn the basics of object-oriented programming with SystemVerilog and build upon that foundation to learn how to design testbenches using the UVM. Use the UVM Primer to brush up on your UVM knowledge before a job interview to be able to confidently answer questions such as "What is a uvm_agent?" , "How do you use uvm_sequences?", and "When do you use the UVM's factory." The UVM Primer's downloadable code examples give you hands-on experience with real UVM code. Ray Salemi uses online videos (on to walk through the code from each chapter and build your confidence. Read The UVM Primer today and start down the path to the UVM. 

Über den Autor und weitere Mitwirkende

Ray Salemi is a senior verification consultant with Mentor Graphics. Salemi started his career in Electronic Design Automation with Gateway Design Automation, the inventors of Verilog. Since then he has worked for Cadence Design Systems, Sun Microsystems, and several startups. Ray Salemi is the author of the popular introduction to simulation, FPGA SIMULATION.


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Die hilfreichsten Kundenrezensionen auf (beta) 5.0 von 5 Sternen  6 Rezensionen
2 von 2 Kunden fanden die folgende Rezension hilfreich
5.0 von 5 Sternen Excellent intro to UVM 25. November 2013
Von Kari - Veröffentlicht auf
Format:Kindle Edition
This UVM primer fills a large void in learning the basic concepts of UVM. While one can take a class or read articles and code snippets on many of the Verification websites, this book is helpful on getting the overall picture which helps to answer the question "why bother with UVM". I highly recommend the book for anyone new to UVM as well as for those who have been using UVM for a while. In Verification it is easy to get too mired up in the details to forget what where you're going and why. The book is concise, easy to read, and even had me chuckling at times. I've been working as an ASIC Design/Verification Engineer for over a decade, have been using UVM for 2 years, and this is one of the best books I've read on the subject. It's highly recommended.
5.0 von 5 Sternen Five Stars 3. Juli 2014
Von Andy He - Veröffentlicht auf
Format:Taschenbuch|Verifizierter Kauf
A really good book help you transit from traditional testbench to UVM testbench.
5.0 von 5 Sternen Excellent introductory book! If you want to know how to go from a Verilog testbench to SystemVerilog testbench, this is it! 9. Juni 2014
Von Ruben Martinez - Veröffentlicht auf
Format:Taschenbuch|Verifizierter Kauf
I had been looking for a book that walked me from a testbench originally written in Verilog and how to evolve it to Systemverilog written in the Universal Verification Methodology (UVM) style. The writing in this primer is easily understood and entertaining. Support is available from the author's website in the form of downloadable SystemVerilog source code from his website. Additional support in the form of videos is also available on Youtube from his channel. To get the most from this book, you should be familiar with Java since SystemVerilog classes and methods are based heavily on Java.

To fill in the necessary gaps, I would recommend "System Verilog for Verification" by Chris Spears as a follow up book.
5.0 von 5 Sternen Very good introduction to UVM 4. Juni 2014
Von Michel ROhner - Veröffentlicht auf
Format:Taschenbuch|Verifizierter Kauf
The book starts by presenting the verification of a small ALU using System Verilog. Then modify the code to end up with the UVM version. This is a good approach to demonstrate the advantage of UVM compared to only System Verilog.
5.0 von 5 Sternen It give me a big picture of UVM 16. Mai 2014
Von Robinson - Veröffentlicht auf
Format:Taschenbuch|Verifizierter Kauf
This books serves the purpose for reader new to UVM and has a great explanation of OOP using SystemVerilog and out-of-the box analogy beyond electronics which really help me understand things better.

I would recommend to those who wanted to learn UVM quickly.
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