- Taschenbuch: 154 Seiten
- Verlag: Morgan and Claypool Publishers (3. Dezember 2007)
- Sprache: Englisch
- ISBN-10: 159829122X
- ISBN-13: 978-1598291223
- Größe und/oder Gewicht: 23,6 x 19,1 x 0,8 cm
- Amazon Bestseller-Rang: Nr. 762.959 in Englische Bücher (Siehe Top 100 in Englische Bücher)
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Produktinformation |
Produktbeschreibungen
Kurzbeschreibung
Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today's microprocessor chips, it is too costly to design and debug ever-larger processors every year or two. CMPs avoid these problems by filling up a processor die with multiple, relatively simpler processor cores instead of just one huge core. The exact size of a CMPs cores can vary from very simple pipelines to moderately complex superscalar processors, but once a core has been selected the CMPs performance can easily scale across silicon process generations simply by stamping down more copies of the hard-to-design, high-speed processor core in each successive chip generation. In addition, parallel code execution, obtained by spreading multiple threads of execution across the various cores, can achieve significantly higher performance than would be possible using only a single core. While parallel threads are already common in many useful workloads, there are still important workloads that are hard to divide into parallel threads. The low inter-processor communication latency between the cores in a CMP helps make a much wider range of applications viable candidates for parallel execution than was possible with conventional, multi-chip multiprocessors; nevertheless, limited parallelism in key applications is the main factor limiting acceptance of CMPs in some types of systems.
Synopsis
Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today's microprocessor chips, it is too costly to design and debug ever-larger processors every year or two. CMPs avoid these problems by filling up a processor die with multiple, relatively simpler processor cores instead of just one huge core.The exact size of a CMPs cores can vary from very simple pipelines to moderately complex superscalar processors, but once a core has been selected the CMPs performance can easily scale across silicon process generations simply by stamping down more copies of the hard-to-design, high-speed processor core in each successive chip generation. In addition, parallel code execution, obtained by spreading multiple threads of execution across the various cores, can achieve significantly higher performance than would be possible using only a single core. While parallel threads are already common in many useful workloads, there are still important workloads that are hard to divide into parallel threads. The low inter-processor communication latency between the cores in a CMP helps make a much wider range of applications viable candidates for parallel execution than was possible with conventional, multi-chip multiprocessors; nevertheless, limited parallelism in key applications is the main factor limiting acceptance of CMPs in some types of systems.
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Concise introduction of recent developments in processor design...
26. November 2008
Workload charectarization and benchmarks are 2 critical components influencing computer system design, as well as processor design. This concise book focuses on the Workload charecterization issues (Throughput sensitive and Latency sensitive workloads), and how they affect processor design. You might have to look up the various benchmarks referred to in this book. At least I had to, as I am not in the business of designing computer systems or processors.
Chapter 1 makes the case of CMT (chip multi-threading architecture). Chapter 2 covers Application workloads may already come with a good degree of threading already exists, and how CMT architecture exploits this property. Chapter 3 covers other considerations where legacy code with little or no direct threading can still exploit the CMT benefits via automatic Thread Level Parallelism from sequential code. It also covers recent techniques where you can get completely automated parallelization of java code. Chapter 4 covers manual programming techniques for exploiting CMT.
For non-practitioner(s) of computer system design or processor design, this concise book definitely helps. Anyone with EE background (curiosity can make up for this too!) to get up to speed with recent trends in processor design. This is important because sooner or later, you will deal with computer systems using these innovations.
Chapter 1 makes the case of CMT (chip multi-threading architecture). Chapter 2 covers Application workloads may already come with a good degree of threading already exists, and how CMT architecture exploits this property. Chapter 3 covers other considerations where legacy code with little or no direct threading can still exploit the CMT benefits via automatic Thread Level Parallelism from sequential code. It also covers recent techniques where you can get completely automated parallelization of java code. Chapter 4 covers manual programming techniques for exploiting CMT.
For non-practitioner(s) of computer system design or processor design, this concise book definitely helps. Anyone with EE background (curiosity can make up for this too!) to get up to speed with recent trends in processor design. This is important because sooner or later, you will deal with computer systems using these innovations.
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